MPC5632MMLL40 datasheet(31/106 Pages) FREESCALE

31 / 106 page

MPC5634M Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

•

2 sources of the serialized data:

— eTPU_A and eMIOS output channels

— Memory-mapped register in the DSPI

•

Destinations for the deserialized data:

— eTPU_A and eMIOS input channels

— SIU External Interrupt Request inputs

— Memory-mapped register in the DSPI

•

Deserialized data is provided as Parallel Output signals and as bits in a memory-mapped register

•

Transfer initiation conditions:

— Continuous

— Edge sensitive hardware trigger

— Change in data

•

Pin serialization/deserialization with interleaved SPI frames for control and diagnostics

•

Continuous serial communications clock

•

Support for parallel and serial chaining of up to four DSPI blocks

2.3.16

eSCI

The enhanced serial communications interface (eSCI) allows asynchronous serial communications with peripheral devices and

other MCUs. It includes special support to interface to Local Interconnect Network (LIN) slave devices. The eSCI block

provides the following features:

•

Full-duplex operation

•

Standard mark/space non-return-to-zero (NRZ) format

•

13-bit baud rate selection

•

Programmable 8-bit or 9-bit, data format

•

Programmable 12-bit or 13-bit data format for Timed Serial Bus (TSB) configuration to support the Microsecond bus

standard

•

Automatic parity generation

•

LIN support

— Autonomous transmission of entire frames

— Configurable to support all revisions of the LIN standard

— Automatic parity bit generation

— Double stop bit after bit error

— 10- or 13-bit break support

•

Separately enabled transmitter and receiver

•

Programmable transmitter output parity

•

2 receiver wake up methods:

— Idle line wake-up

— Address mark wake-up

•

Interrupt-driven operation with flags

•

Receiver framing error detection

•

Hardware parity checking

•

1/16 bit-time noise detection

•

DMA support for both transmit and receive data

— Global error bit stored with receive data in system RAM to allow post processing of errors

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