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TSA0801 Fiches technique(PDF) 4 Page - STMicroelectronics |
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TSA0801 Fiches technique(HTML) 4 Page - STMicroelectronics |
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4 / 20 page ![]() TSA0801 4/20 ELECTRICAL CHARACTERISTICS AVCC = DVCC = VCCB = 2.5V, Fs= 40Msps,Fin=1MHz, Vin@ -1.0dBFS, VREFM = 0V Tamb = 25 °C (unless otherwise specified) TIMING CHARACTERISTICS TIMING DIAGRAM Symbol Parameter Test conditions Min Typ Max Unit FS Sampling Frequency 0.5 40 MHz DC Clock Duty Cycle 45 50 55 % TC1 Clock pulse width (high) 11 12.5 ns TC2 Clock pulse width (low) 11 12.5 ns Tod Data Output Delay (Fall of Clock to Data Valid) 10pF load capacitance 5ns Tpd Data Pipeline delay 6.5 cycles Ton Falling edge of OEB to digital output valid data 1ns Toff Rising edge of OEB to digital output tri-state 1ns N-1 N N+1 N+6 N+7 N+2 N+5 N+3 N+4 N+8 N N+1 N-2 N-3 N-4 N-5 N-6 N-7 N-8 CLK DR Tod Ton Toff 6.5 clk cycles HZ state DATA OUT OEB |
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