AD9520-2SLASHPCBZ datasheet(28/84 Pages) AD

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AD9520-2

Rev. 0 | Page 28 of 84

THEORY OF OPERATION

OPERATIONAL CONFIGURATIONS

The AD9520 can be configured in several ways. These

configurations must be set up by loading the control registers

(see Table 49 to Table 60). Each section or function must be

individually programmed by setting the appropriate bits in the

corresponding control register or registers. When the desired

configuration is programmed, the user can store these values in

the on-board EEPROM to allow the part to power up in the desired

configuration without user intervention.

Mode 0: Internal VCO and Clock Distribution

When using the internal VCO and PLL, the VCO divider must

be employed to ensure that the frequency presented to the channel

dividers does not exceed its specified maximum frequency (see

Table 3). The internal PLL uses an external loop filter to set the

loop bandwidth. The external loop filter is also crucial to the

loop stability.

When using the internal VCO, it is necessary to calibrate the

VCO (0x018[0]) to ensure optimal performance.

For internal VCO and clock distribution applications, the

Table 22. Settings When Using Internal VCO

Description

0x010[1:0] = 00b

PLL normal operation (PLL on)

0x010 to 0x01E

PLL settings; select and enable a reference

input; set R, N (P, A, B), PFD polarity, and ICP

according to the intended loop configuration

0x1E1[1] = 1b

VCO selected as the source

0x01C[2:0]

Enable reference inputs

0x1E0[2:0]

Set VCO divider

0x1E1[0] = 0b

Use the VCO divider as the source for the

distribution section

0x018[0] = 0b

0x232[0] = 1b

Reset VCO calibration and issue IO_UPDATE

(not necessary for the first time after power-

up but must be done subsequently)

0x018[0] = 1b

0x232[0] = 1b

Initiate VCO calibration, issue IO_UPDATE

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