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PSD4235G2 Fiches technique(PDF) 86 Page - STMicroelectronics |
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PSD4235G2 Fiches technique(HTML) 86 Page - STMicroelectronics |
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86 / 93 page ![]() Preliminary Information PSD4000 Series 83 Symbol Parameter 1 Conditions Typical2 Max Unit CIN Capacitance (for input pins only) VIN = 0 V 4 6 pF COUT Capacitance (for input/output pins) VOUT = 0 V 8 12 pF CVPP Capacitance (for CNTL2/VPP)VPP = 0 V 18 25 pF NOTES: 1. These parameters are only sampled and are not 100% tested. 2. Typical values are for TA = 25°C and nominal supply voltages. TA = 25 °C, f = 1 MHz 14.0 Pin Capacitance 15.0 Figure 34. AC Testing Input/Output Waveform 16.0 Figure 35. AC Testing Load Circuit 17.0 Programming 3.0V 0V TEST POINT 1.5V DEVICE UNDER TEST 2.01 V 195 Ω C L = 30 pF (INCLUDING SCOPE AND JIG CAPACITANCE) Upon delivery from ST, the PSD4000 device has all bits in the PLDs and memories in the “1” or high state. The configuration bits are in the “0” or low state. The code, configuration, and PLDs logic are loaded through the procedure of programming. Information for programming the device is available directly from ST. Please contact your local sales representative. (See the last page.) |
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