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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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7733 Fiches technique(PDF) 450 Page - Renesas Technology Corp |
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7733 Fiches technique(HTML) 450 Page - Renesas Technology Corp |
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450 / 940 page  APPLICATIONS 7733 Group User’s Manual 17–43 (4) Precautions 1. The watchdog timer stops counting when the STP instruction is executed. For systems which use the watchdog timer, select “STP instruction disabled” with “STP instruction option” on “MASK ROM ORDER CONFIRMATION FORM.” 2. The watchdog timer stops counting when the WIT instruction is executed after the system clock stop bit at wait state (bit 5 at address 6C16) is set to “1.” 3. The contents of the processor interrupt priority level (IPL) is not initialized in the following cases: q When a value which is the same as the reset vector address’s contents is set to the watchdog timer’s vector address q When a program branches to the destination address at reset in a watchdog timer interrupt routine. Reset of the microcomputer is realized by applying the software reset. 17.3 Watchdog timer |
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