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R8C13 Fiches technique(PDF) 30 Page - Renesas Technology Corp |
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R8C13 Fiches technique(HTML) 30 Page - Renesas Technology Corp |
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30 / 224 page ![]() Rev.1.20 Jan 27, 2006 page 19 of 205 REJ09B0111-0120 R8C/13 Group Figure 5.6 Power-on Reset Operation Vpor1 Vcc min Vdet3 Vdet(3) tw(por1) tw(Vpor1–Vdet) Sampling time(1, 2) Internal reset signal (“L” effective) fRING-S 1 X 32 fRING-S 1 X 32 Vpor2 NOTES: 1. Hold the voltage of the microcomputer operation voltage range (Vccmin or above) within sampling time. 2. A sampling clock is selectable. Refer to “5.4 Voltage Detection Circuit” for details. 3. Vdet shows the voltage detection level of the voltage detection circuit. Refer to “5.4 Voltage Detection Circuit” for details. 4. Refer to Table 16.7, 16.8 for electrical characteristics. tw(por2) tw(Vpor2 –Vdet) RESET Vcc about 5 k Ω within td(P-R) 0.1V to 2.7V VCC 0V 0V RESET 0.8VCC or above |
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