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H8SX/1663R Fiches technique(PDF) 1072 Page - Renesas Technology Corp |
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H8SX/1663R Fiches technique(HTML) 1072 Page - Renesas Technology Corp |
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1072 / 1504 page ![]() Section 21 I 2C Bus Interface 2 (IIC2) Rev. 2.00 Sep. 24, 2008 Page 1040 of 1468 REJ09B0412-0200 Bit Bit Name Initial Value R/W Description 3 SCLO 1 R This bit monitors the SCL output level. When reading and SCLO is 1, the SCL pin outputs a high level. When reading and SCLO is 0, the SCL pin outputs a low level. 2 1 Reserved This bit is always read as 1. 1 IICRST 0 R/W IIC Control Module Reset This bit reset the IIC control module except the I 2C registers. If hang-up occurs because of communication failure during I 2C operation, by setting this bit to 1, the I 2C control module can be reset without initializing the registers. 0 1 Reserved This bit is always read as 1. |
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