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HD64F2149YV Fiches technique(PDF) 605 Page - Renesas Technology Corp

No de pièce HD64F2149YV
Description  Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series
PDF  1075 Pages
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Fabricant  RENESAS [Renesas Technology Corp]
Site Internet  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD64F2149YV Fiches technique(HTML) 605 Page - Renesas Technology Corp

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Section 17 Keyboard Buffer Controller
Rev. 3.00 Jan 18, 2006 page 577 of 1044
REJ09B0280-0300
17.3.6
KBF Setting Timing and KCLK Control
Figure 17.11 shows the KBF setting timing and the KCLK pin states.
KCLK
(pin)
φ*
Internal
KCLK
Falling edge
signal
RXCR3 to
RXCR0
KCLK
(output)
KBF
11th fall
Automatic I/O inhibit
H'000
H'010
Note: * The
φ clock shown here is scaled by 1/N in medium-speed mode when the operating
mode is active mode.
Figure 17.11 KBF Setting and KCLK Automatic I/O Inhibit Generation Timing



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