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HD64F2149YV Fiches technique(PDF) 603 Page - Renesas Technology Corp |
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HD64F2149YV Fiches technique(HTML) 603 Page - Renesas Technology Corp |
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603 / 1075 page ![]() Section 17 Keyboard Buffer Controller Rev. 3.00 Jan 18, 2006 page 575 of 1044 REJ09B0280-0300 17.3.4 KCLKI and KDI Read Timing Figure 17.9 shows the KCLKI and KDI read timing. T1 T2 φ* Internal read signal KCLK, KD (pin state) KCLKI, KDI (register) Internal data bus (read data) Note: * The φ clock shown here is scaled by 1/N in medium-speed mode when the operating mode is active mode. Figure 17.9 KCLKI and KDI Read Timing |
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