H8S2158 datasheet(21/927 Pages) RENESAS

21 / 927 page

Rev. 3.00 Jan 25, 2006 page xxi of lii

Section 8 RAM-FIFO Unit (RFU).................................................................................. 167

8.1

Features ............................................................................................................................. 167

8.2

Register Descriptions ........................................................................................................ 169

8.2.1

FIFO Status/Register/Pointer (FSTR) .................................................................. 169

8.2.2

Base Address Register (BAR).............................................................................. 170

8.2.3

Read Address Pointer (RAR)............................................................................... 170

8.2.4

Write Address Pointer (WAR) ............................................................................. 171

8.2.5

Temporary Pointer (TMP) ................................................................................... 171

8.2.6

Valid Data Byte Number (DATAN) .................................................................... 172

8.2.7

Free Area Byte Number (FREEN)....................................................................... 172

8.2.8

Read Start Address (NRA)................................................................................... 172

8.2.9

Write Start Address (NWA)................................................................................. 173

8.2.10 Data Transfer Control Register A (DTCRA) ....................................................... 173

8.2.11 Data Transfer Control Register B (DTCRB) ....................................................... 175

8.2.12 Data Transfer Status Register C (DTSTRC) ........................................................ 176

8.2.13 Data Transfer ID Register (DTIDR) .................................................................... 178

8.2.14 Data Transfer ID Read/Write Select Register A (DTIDSRA) ............................. 178

8.2.15 Data Transfer ID Read/Write Select Register B (DTIDSRB).............................. 179

8.2.16 Data Transfer Status Register A (DTSTRA)........................................................ 179

8.2.17 Data Transfer Status Register B (DTSTRB)........................................................ 180

8.2.18 Data Transfer Control Register C (DTCRC)........................................................ 180

8.2.19 Data Transfer Control Register D (DTCRD) ....................................................... 181

8.2.20 Data Transfer Interrupt Enable Register (DTIER)............................................... 181

8.2.21 Data Transfer Register Select Register (DTRSR)................................................ 181

8.3

Activation Source and Priority.......................................................................................... 183

8.4

RAM-FIFO Location ........................................................................................................ 184

8.5

RAM-FIFO Pointer ........................................................................................................... 184

8.6

RAM-FIFO Manipulation and RFU Bus Cycles............................................................... 184

8.7

RFU Bus Cycle ................................................................................................................. 188

8.7.1

Clock Division ..................................................................................................... 188

8.7.2

RFU Bus Cycle Insertion ..................................................................................... 189

8.7.3

RFU Response Time ............................................................................................ 189

8.8

Operation........................................................................................................................... 191

8.8.1

Transmission/Reception of Single Data Block .................................................... 191

8.8.2

Transmission/Reception of Consecutive Data Blocks ......................................... 192

8.8.3

RFU Manipulation by USB.................................................................................. 193

8.8.4

RFU Manipulation by SCI ................................................................................... 197

8.8.5

RFU Manipulation by MCIF................................................................................ 200

8.9

Interrupt Sources ............................................................................................................... 202

8.10 RFU Initialization ............................................................................................................. 203

8.11 Usage Notes ...................................................................................................................... 204

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