M32CSLASH8B datasheet(37/406 Pages) RENESAS

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Under development

M32C/8B Group

2. Central Processing Unit (CPU)

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 20 of 385

2.1.8.7

Interrupt Enable Flag (I)

The I flag enables maskable interrupts.

Interrupts are disabled when the I flag is set to 0 and enabled when it is set to 1. The I flag becomes 0 when

an interrupt request is acknowledged.

2.1.8.8

Stack Pointer Select Flag (U)

ISP is selected when the U flag is set to 0. USP is selected when the U flag is set to 1.

The U flag becomes 0 when a hardware interrupt request is acknowledged or the INT instruction specifying

software interrupt numbers 0 to 31 is executed.

2.1.8.9

Processor Interrupt Priority Level (IPL)

IPL is 3 bits wide and assigns processor interrupt priority levels from level 0 to level 7.

If a requested interrupt has higher priority level than IPL, the interrupt is enabled.

2.1.8.10 Reserved Space

Only write 0 to bits assigned to the reserved space. When read, the bits return undefined values.

2.2

High-Speed Interrupt Registers

Registers associated with the high-speed interrupt are as follows:

• Flag save register (SVF)

• PC save register (SVP)

• Vector register (VCT)

Refer to 11.4 High-Speed Interrupt for details.

2.3

DMAC-Associated Registers

Registers associated with the DMAC are as follows:

• DMA mode register (DMD0, DMD1)

• DMA transfer count register (DCT0, DCT1)

• DMA transfer count reload register (DRC0, DRC1)

• DMA memory address register (DMA0, DMA1)

• DMA memory address reload register (DRA0, DRA1)

• DMA SFR address register (DSA0, DSA1)

Refer to 13. DMAC for details.

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