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HD74HC160 Fiches technique(PDF) 7 Page - Renesas Technology Corp |
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HD74HC160 Fiches technique(HTML) 7 Page - Renesas Technology Corp |
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7 / 15 page ![]() HD74HC160, HD74HC161, HD74HC162, HD74HC163 Rev.2.00, Oct 11, 2005 page 7 of 14 Timing Diagram HD74HC160/HD74HC162 Sequence illustrated in waveforms. 1. Clear outputs to zero. 2. Preset to BCD seven. 3. Count to eight, nine, zero, one, two and three. 4. Inhibit (Asynchronous) Clear(HC160) Clear(HC162) Clock(HC160) Ripple Carry Output Clear Load Count 0 9 8 73 2 1 Inhibit Clock(HC162) Enable P Enable T Load Data Inputs Count Enables Outputs A B C D QA QB QC QD (Synchronous) |
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