STV0299B datasheet(16/36 Pages) STMICROELECTRONICS

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STV0299B

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FUNCTIONAL DESCRIPTION (continued)

4.6.3

Synchronization

In DVB, the packet length after inner decoding is

204. The sync word is the first byte of each

packet. Its value is Hex 47, but this value is

complemented every 8 packets. In DSS, the

packet length is 147 and the sync word is Hex 1D.

An Up/Down Sync counter counts whenever a

sync word is recognized with the correct timing,

and counts down during each missing sync word.

This counter is bounded by a programmable

maximum - when this value is reached, the LK bit

(“locked”) is set in the VSTATUS register. When

the event counter counts down to until 0, this flag

is reset.

4.6.4

Error Monitoring

A 16-bit counter, ERRCNT, allows the counting of

errors at different levels. ERRCNT is fed either by:

• the input QPSK bit errors (that are corrected by

the Viterbi decoder), or,

• the bit, or,

• the byte error (that are corrected by the

Reed-Solomon decoder), or,

• the packet error (not corrigible, leading to a

pulse at the ERROR output).

The content of ERRCNT may be transferred to the

read only registers ERRCNT_LOW (LSB) and

ERRCNT_HIGH (MSB).

Two functional modes are proposed, depending

on a control register bit:

1 Error Mode = 0. This is an error rate measure,

that tells the number of errors occurring within

a specified number of output bytes, NB. NB has

four possible values given in the Error Control

state of the error counter is transferred to a

16-bit register, then the error counter is reset.

The Error Count Registers in Addresses 1D

and 1E may be read by the microprocessor via

I2C bus. Two ways of reading may be used:

16-bit reading, starting with MSB, or 8-bit

reading (LSB only or MSB only).

2 Error Mode = 1. The error counter just counts

the error; the I2C register permanently copies

the content of the error counter. When the MSB

byte is read, the error counter is reset. In both

modes, the 16-bit counter is saturated to its

maximum value.

4.6.5

Convolutional Deinterleaver

In DVB, the convolutional deinterleaver is 17 x 12.

The periodicity of 204 bytes per sync byte is

retained. In DSS, the convolutional deinterleaver

is 146 x 13, and there is also a periodicity of

147 bytes per sync byte. The deinterleaver may

be bypassed - for details, see Section 4.6.6

‘Reed-Solomon Decoder and Descrambler’.

4.6.6

Reed-Solomon Decoder and

Descrambler

The input blocks are 204-byte long with 16 parity

bytes in DVB. The synchro byte is the first byte of

the block. Up to 8 byte errors may be fixed.

The Code Generator polynomial is:

over the Galois Field generated by:

Energy dispersal descrambler and output energy

dispersal descrambler generator:

The polynomial is initialized every eight blocks

with the sequence 100101010000000.

The synchro words are unscrambled and the

scrambler is reset every 8 packets.

The output interface may be forced into high

impedance mode by setting bit 0 of Address 28.

Doing

this

affects

the

D[7:0],

CLK_OUT,

STR_OUT, D/P and ERROR pins. This also allows

for board testing, and “OR” wiring several link

circuits (for example, cable links). The output

stream is either parallel (byte stream) or serial (bit

stream) depending on bit 1 of Address 28.

The outputs are controlled by the RS Control

4.6.7

Parallel Output Interface

A schematic diagram of the parallel output

interface is shown in Figure 7. The parallel output

format is compliant with the DVB common

interface protocol.

When the SYNC is not found (LK = 0 in the status

of the DVB common interface standard) remains

at a low level.

CLK_OUT has a duty cycle between 40 and 60%.

()

–

() x ω

–

() …

…

() x ω

–

()

+++

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