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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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M306V2EEFS Fiches technique(PDF) 174 Page - Renesas Technology Corp |
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M306V2EEFS Fiches technique(HTML) 174 Page - Renesas Technology Corp |
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174 / 271 page  Rev.1.40 Oct 06, 2004 page 174 of 269 M306V2ME-XXXFP, M306V2EEFP 2.14.10 Data Clock Generating Circuit This circuit generates a data clock synchronized with the start bit detected in the start bit detecting circuit. The data clock stores caption data to the 16-bit shift register. When the 16-bit data has been stored and the clock run-in determination circuit determines clock run-in, the caption data latch completion flag is set. This flag is reset at a falling of the vertical synchronous signal (Vsep). Figure 2.14.11 Data clock position register b7 b6 b5 b4 b3 b2 b1 b0 Data clock position register Data clock position set bits Nothing is assigned. If an attempt to write to these bits, write “0.” The read turns out to be “0.” Function Bit name R W Bit symbol DPS0 Symbol Address When reset DPS 026A16 XXX000012 DPS1 DPS2 DPS3 DPS4 2.14.11 16-bit Shift Register The caption data converted into a digital value by the comparator is stored into the 16-bit shift register in synchronization with the data clock. The contents of the stored caption data can be obtained by reading out the caption data register 1 (addresses 026316, 026216) and caption data register 2 (addresses 026516, 026416). These registers are reset to “0” at a falling of Vsep. Read out data registers 1 and 2 after the occurrence of a data slicer interrupt (refer to “2.14.12 Interrupt request generating circuit)”. |
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