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6V7 Fiches technique(PDF) 4 Page - Renesas Technology Corp |
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6V7 Fiches technique(HTML) 4 Page - Renesas Technology Corp |
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4 / 298 page ![]() Rev.1.00 May 18, 2004 page 4 of 296 M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP 1.4 Block Diagram Figure 1.4.1 is a block diagram. Figure 1.4.1 Block diagram Timer Timer TA0 (16 bits) Timer TA1 (16 bits) Timer TA2 (16 bits) Timer TA3 (16 bits) Timer TA4 (16 bits) Timer TB0 (16 bits) Timer TB1 (16 bits) Timer TB2 (16 bits) Internal peripheral functions I/O ports Port P0 8 Port P1 8 Port P2 8 Port P3 8 Port P4 8 Port P5 8 Port P6 5 Watchdog timer (15 bits) DMAC (2 channels) D-A converter (8 bits X 2 channels) M16C/60 series16-bit CPU core R0L R0H R1HR1L R2 R3 A0 A1 FB R0L R0H R1HR1L R2 R3 A0 A1 FB Registers ISP USP Stack pointer Vector table INTB Multiplier Memory ROM (Note 1) (Note 2) RAM SB FLG PC Program counter A-D converter OSD System clock generator XIN–XOUT Data slicer0 UART0/clock synchronous SI/O HSYNC counter Multi-master I2C-bus interface 0 UART2/clock synchronous SI/O Multi-master I2C-bus interface 1 Data slicer1 Note 1. ROM capacity changes with kinds. Note 2. RAM capacity changes with kinds. |
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