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HD74LS190P Fiches technique(PDF) 9 Page - Renesas Technology Corp |
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HD74LS190P Fiches technique(HTML) 9 Page - Renesas Technology Corp |
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9 / 11 page ![]() HD74LS190 Rev.3.00, Jul.15.2005, page 9 of 10 Waveforms 4 Clock →Q Load Data Down/Up Clock Q Enable = 0V 1.3V 1.3V 1.3V 1.3V tPHL tPLH VOH VOL 0V 3V 0V 3V 0V 3V 0V 3V Notes: 1. When test the QA, QB, and QC outputs, data inputs A, B and C are shown by the solid line, and data input D is shown by the dashed line. 2. When test the QD output, data inputs A and D are shown by the solid line, and data inputs B and C are held at the low logic level. Waveforms 5 Clock →Max / Min Load Inputs A B, C, D Down/Up Clock Max/Min Enable = 0V 1.3V 1.3V 1.3V 1.3V tPHL tPLH VOH VOL 0V 3V 0V 3V 0V 3V 0V 3V 0V 3V 1.3V 1.3V 1.3V 1.3V tPHL tPLH Note: Data inputs B and C are shown by the dashed line. Data input D is shown by the solid line. |
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