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HD74LS162AFPEL Fiches technique(PDF) 5 Page - Renesas Technology Corp |
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HD74LS162AFPEL Fiches technique(HTML) 5 Page - Renesas Technology Corp |
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5 / 11 page ![]() HD74LS162A Rev.3.00, Jul.15.2005, page 5 of 10 Timing Method Enable P or T Clear Clock Load 1.3V 1.3V 1.3V 1.3V 1.3V 1.3V 1.3V 1.3V 1.3V 1.3V tsu tw (CK) th tsu th tsu th 0V 3V 0V 3V 0V 3V 0V 3V Data Outputs A to D 1.3V 1.3V tsu th 0V 3V Testing Method Test Circuit 4.5V QA Load circuit 1 Output QA VCC RL CL Input P.G. Zout = 50 Ω Input P.G. Zout = 50 Ω A B C D CK P T CLR Load QC QD QB Same as Load Circuit 1. Output QB Same as Load Circuit 1. Output QC Same as Load Circuit 1. Output QD Ripple Carry Ripple Carry Same as Load Circuit 1. Notes: 1. CL includes probe and jig capacitance. 2. All diodes are 1S2074(H). |
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