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PSD835G2-70UI Fiches technique(PDF) 91 Page - STMicroelectronics

No de pièce PSD835G2-70UI
Description  Configurable Memory System on a Chip for 8-Bit Microcontrollers
PDF  110 Pages
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Fabricant  STMICROELECTRONICS [STMicroelectronics]
Site Internet  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

PSD835G2-70UI Fiches technique(HTML) 91 Page - STMicroelectronics

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PSD8XX Family
PSD835G2
90
-90
-12
Turbo
Symbol
Parameter
Conditions
Min
Max
Min
Max
Off
Unit
tLVLX
ALE or AS Pulse Width
22
24
ns
tAVLX
Address Setup Time
(Note 3)
7
9
ns
tLXAX
Address Hold Time
(Note 3)
8
10
ns
tAVQV
Address Valid to Data Valid
(Note 3)
90
120
Add 20**
ns
t SLQV
CS Valid to Data Valid
90
120
ns
RD to Data Valid
(Note 5)
35
35
ns
t RLQV
RD or PSEN to Data Valid,
80C51XA Mode
(Note 2)
45
48
ns
t RHQX
RD Data Hold Time
(Note 1)
0
0
ns
tRLRH
RD Pulse Width
(Note 1)
36
40
ns
tRHQZ
RD to Data High-Z
(Note 1)
38
40
ns
tEHEL
E Pulse Width
38
42
ns
tTHEH
R/W Setup Time to Enable
10
16
ns
tELTL
R/W Hold Time After Enable
0
0
ns
tAVPV
Address Input Valid to
(Note 4)
30
35
ns
Address Output Delay
Read Timing (3.0 V to 3.6 V Versions)
Microcontroller Interface – PSD835G2 AC/DC Parameters
(3.0 V to 3.6 V Versions)
NOTES: 1. RD timing has the same timing as DS and PSEN signals.
2. RD and PSEN have the same timing for 80C51.
3. Any input used to select an internal PSD835G2V function.
4. In multiplexed mode latched address generated from ADIO delay to address output on any Port.
5. RD timing has the same timing as DS.



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