33784 datasheet(15/30 Pages) FREESCALE

15 / 30 page

Analog Integrated Circuit Device Data

Freescale Semiconductor

33784

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

Figure 6. DBUS Slave Logic Block Diagram

COMMUNICATION FORMAT

DBUS messages are composed of individual words

separated by a frame delay. Transfers are full duplex.

Command messages from the master occur at the same time

as responses from the slaves. Slave responses to commands

occur during the next command message. This allows slaves

time to decode the command, retrieve the information, and

prepare to send it to the master. A bus traffic example is

shown in Figure 7.

The example shows three commands separated by the

minimum frame delay followed by a command after a longer

delay.

Figure 7. Bus Traffic Example

Bus Controller

10MHz Clock

Command Buffer

CRC

Check

Latch

Data

Data Clock

Load Enable

Response Shifter

CRC Generator

Data Clock

SEL

IResponse ON

10MHz Clock

Received Message

From MASTER

DBUS Registers

INIT

REQ STATUS

REQ AN0

I/O CONTROL

REQ ID

REQ AN1

CLEAR

FORMAT CONTROL

TEST

DATA OUT [2:0]

I/O [2:0]

AD_SEL

AD_DATA [9:0]

33784 Fiches technique(PDF) 15 Page - Freescale Semiconductor, Inc

33784 Fiches technique(HTML) 15 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

Fiches technique Télécharger

Lien URL