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M95256_0807 Fiches technique(PDF) 15 Page - STMicroelectronics

No de pièce M95256_0807
Description  256 Kbit serial SPI bus EEPROM with high-speed clock
PDF  44 Pages
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Fabricant  STMICROELECTRONICS [STMicroelectronics]
Site Internet  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

M95256_0807 Fiches technique(HTML) 15 Page - STMicroelectronics

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M95256, M95256-W, M95256-R
Instructions
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5.2
Write Disable (WRDI)
One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction
to the device.
As shown in Figure 7, to send this instruction to the device, Chip Select (S) is driven low,
and the bits of the instruction byte are shifted in, on Serial Data input (D).
The device then enters a wait state. It waits for a the device to be deselected, by Chip Select
(S) being driven high.
The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events:
●
Power-up
●
WRDI instruction execution
●
WRSR instruction completion
●
WRITE instruction completion.
Figure 7.
Write Disable (WRDI) sequence
C
D
AI03750D
S
Q
2
1
34567
High Impedance
0
Instruction



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