STPCE1EEBC datasheet(75/87 Pages) STMICROELECTRONICS

75 / 87 page

DESIGN GUIDELINES

Release 1.3 - January 29, 2002

75/87

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

6.4.3. PCI INTERFACE

6.4.3.1. Introduction

In order to achieve a PCI interface which work at

clock

frequencies

33MHz,

careful

consideration has to be given to the timing of the

interface with all the various electrical and

physical constraints taken into consideration.

6.4.3.2. PCI Clocking Scheme

The PCI Clocking Scheme deserves a special

mention here. Basically the PCI clock (PCICLKO)

is generated on-chip from HCLK through a

programmable delay line and a clock divider. The

nominal frequency is 33MHz. This clock must be

looped to PCICLKI and goes to the internal South

Bridge through a deskewer. On the contrary, the

internal North Bridge is clocked by HCLK, putting

some additionnal constraints on T0 and T1.

Figure 6-21. Clock Scheme

HCLK PLL

1/2

1/3

1/4

clock

Strap Options

PCICLKO

PCICLKI

HCLK

AD[31:0]

South

North

Deskewer

MUX

delay

STPC

MD[30:27]

MD[17,4]

MD[7:6]

Bridge

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