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T84C5112-RKREV Fiches technique(PDF) 66 Page - ATMEL Corporation |
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T84C5112-RKREV Fiches technique(HTML) 66 Page - ATMEL Corporation |
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66 / 97 page ![]() 66 Rev. B - November 10, 2000 Preliminary T80C5112 A low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-priority interrupt. A high-priority interrupt canÕt be interrupted by any other interrupt source. If two interrupt requests of different priority levels are received simultaneously, the request of higher priority level is serviced. If interrupt requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. Thus within each priority level there is a second priority structure determined by the polling sequence. Table 40. Priority bit level values IPH.x IP.x Interrupt Level Priority 0 0 0 (Lowest) 0 1 1 1 0 2 1 1 3 (Highest) Table 41. Address vectors Interrupt Name Interrupt Address Vector Priority Number external interrupt (INT0) 0003h 1 Timer0 (TF0) 000Bh 2 external interrupt (INT1) 0013h 3 Timer1 (TF1) 001Bh 4 PCA (CF or CCFn) 0033h 5 UART (RI or TI) 0023h 6 SPI 004Bh 8 ADC 0043h 9 |
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