C167CS-L datasheet(59/81 Pages) INFINEON

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C167CS-4R

C167CS-L

Data Sheet

V2.2, 2001-08

AC Characteristics

Definition of Internal Timing

The internal operation of the C167CS is controlled by the internal CPU clock

fCPU. Both

edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles)

operations.

The specification of the external timing (AC Characteristics) therefore depends on the

time between two consecutive edges of the CPU clock, called “TCL” (see Figure 11).

Figure 11

Generation Mechanisms for the CPU Clock

The CPU clock signal

fCPU can be generated from the oscillator clock signal fOSC via

different mechanisms. The duration of TCLs and their variation (and also the derived

external timing) depends on the used mechanism to generate

fCPU. This influence must

be regarded when calculating the timings for the C167CS.

Note: The example for PLL operation shown in Figure 11 refers to a PLL factor of 4.

The used mechanism to generate the basic CPU clock is selected by bitfield CLKCFG

in register RP0H.7-5.

Upon a long hardware reset register RP0H is loaded with the logic levels present on the

upper half of PORT0 (P0H), i.e. bitfield CLKCFG represents the logic levels on pins

MCT04338

OSC

CPU

Phase Locked Loop Operation

TCL

OSC

CPU

Direct Clock Drive

OSC

CPU

Prescaler Operation

TCL

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