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ADE7166 Fiches technique(PDF) 60 Page - Analog Devices

No de pièce ADE7166
Description  Single-Phase Energy Measurement IC with 8052 MCU, RTC and LCD driver
PDF  148 Pages
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Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
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ADE7166 Fiches technique(HTML) 60 Page - Analog Devices

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ADE75xx/ADE71xx
Preliminary Technical Data
Rev. PrE | Page 60 of 148
maintained at 0 when no power is being consumed.
The 256 LSBs (VAROS = 0x100) written to the reactive power
offset register are equivalent to 1 LSB in the waveform sample
register.
Sign of Reactive Power Calculation
Note that the average reactive power is a signed calculation. The
phase shift filter has –90° phase shift when the integrator is
enabled, and +90° phase shift when the integrator is disabled.
Table 42 summarizes the relationship between the phase differ-
ence between the voltage and the current and the sign of the
resulting VAR calculation.
Table 42. Sign of Reactive Power Calculation
Angle
Integrator
Sign
Between 0° to 90°
Off
Positive
Between –90° to 0°
Off
Negative
Between 0° to 90°
On
Positive
Between –90° to 0°
On
Negative
Reactive power sign detection
The ADE75XX/ADE71XX detects a change of sign in the
reactive power. A sign change can be monitored on the filtered
reactive power signal or on a per CF pulse basis, depending on
the configuration of the CFSIGN_OPT bit in the GAIN register
(0x1B). The VARSIGN flag in the Interrupt Status Register 1
SFR (MIRQSTL, 0xDC) record when a change of sign according
to bit VARSIGN in the ACCMODE register (0x0F) has
occurred. If the VARSIGN bit is set in the Interrupt Enable
Register 1 SFR (MIRQENL, 0xD9), the 8052 core has a pending
ADE interrupt. The ADE interrupt stays active until the
VARSIGN status bit is cleared—see Energy measurement
interrupts section.
When VARSIGN in the ACCMODE register (0x0F) is cleared
(default), the VARSIGN flag in the Interrupt Status Register 1
SFR (MIRQSTL, 0xDC) will be set when a transition from
positive to negative reactive power has occurred.
When VARSIGN in the ACCMODE register (0x0F) is set, the
VARSIGN flag in the Interrupt Status Register 1 SFR
(MIRQSTL, 0xDC) will be set when a transition from negative
to positive reactive power has occurred.
Reactive power no-Load detection
The ADE75XX/ADE71XX includes a no-load threshold feature
on the reactive energy that eliminates any creep effects in the
meter. The ADE75XX/ADE71XX accomplishes this by not
accumulating reactive energy if the multiplier output is below
the no-load threshold. When the reactive power is below the
no-load threshold, the RNOLOAD flag in the Interrupt Status
Register 1 SFR (MIRQSTL, 0xDC) is set. If the RNOLOAD bit is
set in the Interrupt Enable Register 1 SFR (MIRQENL, 0xD9),
the 8052 core has a pending ADE interrupt. The ADE interrupt
stays active until the RNOLOAD status bit is cleared—see
Energy measurement interrupts section.
The No-load threshold level is selectable by setting bits
RNOLOAD in the NLMODE register (0x0E). Setting these bits
to 0b00 disable the no-load detection and setting them to 0b01,
0b10 or 0b11 set the no-load detection threshold to 0.015%,
0.0075% and 0.0037% of the full-scale output frequency of the
multiplier respectively.
VARGAIN[11:0]
VARDIV[7:0]
LPF2
CURRENT
CHANNEL
VOLTAGE
CHANNEL
TIME (nT)
5
CLKIN
T
REACTIVE POWER
SIGNAL
+
+
VARHR[23:0]
OUTPUTS FROM THE LPF2 ARE
ACCUMULATED (INTEGRATED) IN
THE INTERNAL REACTIVE ENERGY REGISTER
UPPER 24 BITS ARE
ACCESSIBLE THROUGH
VARHR[23:0] REGISTER
23
0
48
0
WAVEFORM
REGISTER
VALUES
%
VAROS[15:0]
26
sgn
25
2-6 2-7 2-8
+
+
FOR WAVEF0RM
SAMPLING
HPF
90° PHASE
SHIFTING FILTER
Π
2
PHCAL[7:0]
TO
DIGITAL TO FREQUENCY
CONVERTER
Figure 45. ADE75XX/ADE71XX Reactive Energy Calculation



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