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EM640FP16 Fiches technique(PDF) 6 Page - Emerging Memory & Logic Solutions Inc |
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EM640FP16 Fiches technique(HTML) 6 Page - Emerging Memory & Logic Solutions Inc |
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6 / 11 page ![]() EM640FP16 Series Low Power, 256Kx16 SRAM 6 tRC Address CS1 CS2 UB,LB OE Data Out tCO tOH tBA tOE High-Z tBHZ tOHZ tWHZ TIMING WAVEFORM OF READ CYCLE(2) (WE = VIH) Data Valid tOLZ tBLZ tLZ tAA tHZ tRC Address tAA Data Valid tOH Previous Data Valid TIMING WAVEFORM OF READ CYCLE(1). (Address Controlled, CS1=OE=V IL, CS2=WE=VIH, UB or/and LB=VIL) Data Out TIMING DIAGRAMS NOTES (READ CYCLE) 1. tHZ and tOHZ are defined as the outputs achieve the open circuit conditions and are not referanced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. |
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