EM620FV8AS datasheet(8/11 Pages) EMLSI

No de pièce	EM620FV8AS

Description	256K x8 bit Super Low Power and Low Voltage Full CMOS Static RAM

PDF	11 Pages

Scroll/Zoom	100%

Fabricant	EMLSI [Emerging Memory & Logic Solutions Inc]

Site Internet	http://www.emlsi.com

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8 / 11 page

EM620FV8AS Series

Low Power, 256Kx8 SRAM

merging Memory & Logic Solutions Inc.

Rev 0.2

tWC

Address

CS1

CS2

Data in

Data out

CW(2)

tWR(4)

tAW

WP(1)

TIMING WAVEFORM OF WRITE CYCLE(3) ( CS2 CONTROLLED)

High-Z

Data Valid

NOTES (WRITE CYCLE)

1. A write occurs during the overlap(tWP) of low CS1, a high CS2 and low WE. A write begins at the latest

transition among CS1 goes low, CS2 goes high and WE goes low. A write ends at the earliest transition

when CS1 goes high, CS2 goes hagh and WE goes high. The tWP is measured from the beginning of write

to the end of write.

2. tCW is measured from the CS1 going low to end of write.

3. tAS is measured from the address valid to the beginning of write.

4. tWR is measured from the end or write to the address change. tWR applied in case a write ends as CS1 or WE

going high.

tAS(3)

EM620FV8AS Fiches technique(PDF) 8 Page - Emerging Memory & Logic Solutions Inc