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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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ST7SUPERLITE Fiches technique(PDF) 31 Page - STMicroelectronics |
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ST7SUPERLITE Fiches technique(HTML) 31 Page - STMicroelectronics |
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31 / 122 page  ST7LITE0, ST7SUPERLITE 31/122 SYSTEM INTEGRITY MANAGEMENT (Cont’d) 7.5.3 Low Power Modes 7.5.3.1 Interrupts The AVD interrupt event generates an interrupt if the corresponding Enable Control Bit (AVDIE) is set and the interrupt mask in the CC register is re- set (RIM instruction). Mode Description WAIT No effect on SI. AVD interrupts cause the device to exit from Wait mode. HALT The CRSR register is frozen. The AVD remains active but the AVD inter- rupt cannot be used to exit from Halt mode. Interrupt Event Event Flag Enable Control Bit Exit from Wait Exit from Halt AVD event AVDF AVDIE Yes Yes 1 |
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