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ST72324 Fiches technique(PDF) 62 Page - STMicroelectronics |
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ST72324 Fiches technique(HTML) 62 Page - STMicroelectronics |
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62 / 161 page ![]() ST72324 62/161 16-BIT TIMER (Cont’d) Figure 37. Counter Timing Diagram, internal clock divided by 2 Figure 38. Counter Timing Diagram, internal clock divided by 4 Figure 39. Counter Timing Diagram, internal clock divided by 8 Note: The MCU is in reset state when the internal reset signal is high, when it is low the MCU is running. CPU CLOCK FFFD FFFE FFFF 0000 0001 0002 0003 INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) FFFC FFFD 0000 0001 CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) FFFC FFFD 0000 |
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