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ST6369 Fiches technique(PDF) 45 Page - STMicroelectronics |
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ST6369 Fiches technique(HTML) 45 Page - STMicroelectronics |
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45 / 71 page ![]() D7-D5. These bits are not used. VSYNC. This bit reads the status of the VSYNC pin. It is inverted with respect to the pin. HSYNC. This bit reads the status of the HSYNC latch. If a signal has been latched this bit will be high. AD2-AD0. These bits store the real time conver- sion of the value present on the AD input pin. Un- defined reset value. D7, D6, D5, D4, D3. These bits are not used. ADRR AD Result Register (E4H, Read Only) D7 D6 D5 D4 D3 D2 D1 D0 AD2-AD0 A/D = Conv Result HSYNC VSYNC Unused Figure 53. A/D, HSYNC and VSYNC Result Register OCR Outputs Control Register (E5H, Write Only) D7 D6 D5 D4 D3 D2 D1 D0 O0 Data bit O1 Data bit A/D Shift Bit Unuse d Figure 54. Outputs Control Register A/D COMPARATOR (Continued) A/D Shift. This bit determines the voltage range of the AFC input. Writing a zero will select the 0.5V to 4.5V range. Writing a one will select the 1.0V to 5.0V range. Undefined after reset. O1,O0. These bits control the output pins O1,O0. They are undefined after reset. ® ST6369 41/67 |
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