ST62T18C datasheet(31/82 Pages) STMICROELECTRONICS

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ST62T18C/E18C

INTERRUPTS (Cont’d)

Interrupt Polarity Register (IPR)

Address: DAh

—

Read/Write

In conjunction with I/O register ESB bit, the polarity

of I/O pins triggered interrupts can be selected by

setting accordingly the Interrupt Polarity Register

(IPR). If a bit in IPR is set to one the corresponding

port interrupt is inverted (e.g. IPR bit 2 = A; port C

generates interrupt on rising edge. At reset, IPR is

cleared and all port interrupts are not inverted (e.g.

Port C generates interrupts on falling edges).

Bit 7 - Bit 4 =

Unused.

Bit 3 =

Port D Interrupt Polarity.

Bit 2 = Unused.

Bit 1=

Port A Interrupt Polarity.

Bit 0 =

Port B Interrupt Polarity.

Tables 11. I/O Interrupts selections according to IPR, IOR programming

PortD

PortA PortB

GEN

IPR3

IPR0

IOR5

Port B occurrence

Port D occurrence

Interrupt

source

falling edge

rising edge

falling edge

rising edge

falling edge

rising edge

falling edge

rising edge

falling edge

Disabled

GEN

IPR1

IOR6

Port A occurrence

Interrupt

source

falling edge

low level

rising edge

high level

Disabled

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