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M48T08 Fiches technique(PDF) 9 Page - STMicroelectronics

No de pièce M48T08
Description  5V, 64Kbit (8 Kb x 8) TIMEKEEPER짰 SRAM
PDF  30 Pages
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Fabricant  STMICROELECTRONICS [STMicroelectronics]
Site Internet  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

M48T08 Fiches technique(HTML) 9 Page - STMicroelectronics

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M48T08, M48T08Y, M48T18
Operation modes
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data will be available after the latter of the Chip Enable Access times (tE1LQV or tE2HQV) or
Output Enable Access time (tGLQV).
The state of the eight three-state Data I/O signals is controlled by E1, E2 and G. If the
outputs are activated before tAVQV, the data lines will be driven to an indeterminate state
until tAVQV. If the address inputs are changed while E1, E2 and G remain active, output data
will remain valid for Output Data Hold time (tAXQX) but will go indeterminate until the next
address access.
Figure 5.
Read mode AC waveforms
Note:
WRITE Enable (W) = High.
AI00962
tAVAV
tAVQV
tAXQX
tE1LQV
tE1LQX
tE1HQZ
tGLQV
tGLQX
tGHQZ
VALID
A0-A12
E1
G
DQ0-DQ7
tE2HQV
tE2HQX
VALID
tE2LQZ
E2



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