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Table 3. LQFP32/DIP32 Device Pin Description

Pin n°

Pin Name

Level

Port

Main

function

(after

reset)

Alternate function

Input

Output

VAREF

Analog Reference Voltage for ADC

VSSA

Analog Ground Voltage

PF0/MCO/AIN8

I/O CT

ei1

Port F0

Main clock out

(fOSC/2)

ADC Analog

Input 8

PF1 (HS)/BEEP

I/O CT HS

ei1

Port F1

Beep signal output

PF4/OCMP1_A/

AIN10

I/O CT

Port F4

Timer A Output

Compare 1

ADC Analog

Input 10

PF6 (HS)/ICAP1_A

I/O CT HS

Port F6

Timer A Input Capture 1

710

PF7 (HS)/

EXTCLK_A

I/O CT HS

Port F7

Timer A External Clock Source

811

PC0/OCMP2_B/

AIN12

I/O CT

Port C0

Timer B Output

Compare 2

ADC Analog

Input 12

912

PC1/OCMP1_B/

AIN13

I/O CT

Port C1

Timer B Output

Compare 1

ADC Analog

Input 13

PC2 (HS)/ICAP2_B I/O CT HS

Port C2

Timer B Input Capture 2

PC3 (HS)/ICAP1_B I/O CT HS

Port C3

Timer B Input Capture 1

PC4/MISO/ICCDA-

I/O CT

Port C4

SPI Master In /

Slave Out Data

ICC Data Input

PC5/MOSI/AIN14

I/O CT

Port C5

SPI Master Out /

Slave In Data

ADC Analog

Input 14

PC6/SCK/ICCCLK

I/O CT

Port C6

SPI Serial Clock

ICC Clock

Output

PC7/SS/AIN15

I/O CT

Port C7

SPI Slave Select

(active low)

ADC Analog

Input 15

PA3 (HS)

I/O CT HS

ei0

Port A3

PA4 (HS)

I/O CT HS

Port A4

PA6 (HS)/SDAI

I/O CT HS

TPort A6

I2C Data 1)

PA7 (HS)/SCLI

I/O CT HS

TPort A7

I2C Clock 1)

VPP/ ICCSEL

Must be tied low. In flash programming

mode, this pin acts as the programming

voltage input VPP. See Section 12.9.2 for

more details. High voltage must not be ap-

plied to ROM devices

RESET

I/O CT

Top priority non maskable interrupt.

VSS_2

Digital Ground Voltage

OSC23)

I/O

Resonator oscillator inverter output

OSC13)

External clock input or Resonator oscillator

inverter input

VDD_2

Digital Main Supply Voltage

PE0/TDO

I/O CT

Port E0

SCI Transmit Data Out

PE1/RDI

I/O CT

Port E1

SCI Receive Data In

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