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74LVC3G34GD Fiches technique(PDF) 3 Page - Nexperia B.V. All rights reserved |
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74LVC3G34GD Fiches technique(HTML) 3 Page - Nexperia B.V. All rights reserved |
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3 / 21 page ![]() © Nexperia B.V. 2017. All rights reserved 74LVC3G34 All information provided in this document is subject to legal disclaimers. Product data sheet Rev. 12 — 15 December 2016 3 of 21 Nexperia 74LVC3G34 Triple buffer 5. Functional diagram 6. Pinning information 6.1 Pinning Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate) Fig 4. Pin configuration SOT505-2 and SOT765-1 Fig 5. Pin configuration SOT833-1, SOT1089, SOT1116 and SOT1203 |
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