74LVC161

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Product data sheet

Rev. 6 — 30 September 2013

5 of 22

NXP Semiconductors

74LVC161

Presettable synchronous 4-bit binary counter; asynchronous reset

Typical timing sequence: reset outputs to zero; preset to binary twelve; count to thirteen, fourteen, fifteen, zero, one and two;

inhibit.

Fig 7.

Timing sequence

mna909

CP

PE

TC

MR

inhibit

count

CEP

CET

D0

D2

D1

D3

Q0

Q2

Q1

Q3

reset

preset

12

13

14

15

0

1

2