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74HCT03DB Fiches technique(PDF) 7 Page - Nexperia B.V. All rights reserved |
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74HCT03DB Fiches technique(HTML) 7 Page - Nexperia B.V. All rights reserved |
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7 / 14 page ![]() 74HC_HCT03 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 4 — 27 November 2015 7 of 14 NXP Semiconductors 74HC03; 74HCT03 Quad 2-input NAND gate; open-drain output Test data is given in Table 9. Definitions test circuit: RT = termination resistance should be equal to output impedance Zo of the pulse generator. CL = load capacitance including jig and probe capacitance. Fig 7. Test circuit for measuring switching times Table 9. Test data Type Input Load S1 position VI tr, tf CL RL tPZL, tPLZ 74HC03 VCC 6ns 15pF, 50pF 1k VCC 74HCT03 3.0 V 6 ns 15 pF, 50 pF 1 k VCC |
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