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ADG526ATCHIPS Fiches technique(PDF) 13 Page - Analog Devices

No de pièce ADG526ATCHIPS
Description  CMOS Latched 8-/16-Channel Analog Multiplexers
PDF  20 Pages
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Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
Logo AD - Analog Devices

ADG526ATCHIPS Fiches technique(HTML) 13 Page - Analog Devices

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ADG526A/ADG527A
Rev. C | Page 13 of 20
TIMING
Figure 13 shows the timing sequence for latching the switch
address and enable inputs. The latches are level sensitive;
therefore, while WR is held low, the latches are transparent and
the switches respond to the address and enable inputs. This
input data is latched on the rising edge of WR.
3V
0V
3V
0V
WR
EN, A0, A1,
A2, (A3)
1.5V
2.0V
0.8V
tW
tS
tH
Figure 13. Timing Sequence
Figure 14 shows the reset pulse width, tRS, and reset turn-off
time, tOFF (RS).
Note that all digital input signal rise and fall times are measured
from 10% to 90% of 3 V, tR = tF = 20 ns.
tRS
tOFF (RS)
3V
0V
VO
0V
RS
0.8V
1.5V
SWITCH
OUTPUT
Figure 14. Reset Pulse



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