AD5273BRJZ100-R2 datasheet(18/20 Pages) AD

18 / 20 page

AD5273

Data Sheet

Rev. J | Page 18 of 20

APPLICATIONS INFORMATION

DAC

It is common to buffer the output of the digital potentiometer as

a DAC. The buffer minimizes the load dependence and delivers

higher current to the load, if needed.

Figure 43. Programmable Voltage Reference (DAC)

PROGRAMMABLE VOLTAGE SOURCE WITH

BOOSTED OUTPUT

For applications that require high current adjustment, such as a

laser diode driver or tunable laser, consider a booster voltage

source, as shown in Figure 44.

Figure 44. Programmable Booster Voltage Source

In this circuit, the inverting input of the op amp forces the

VOUT to be equal to the wiper voltage set by the digital potenti-

ometer. The load current is then delivered by the supply via the

N-Channel FET, N1. N1 power handling must be adequate to

dissipate (VIN − VOUT) × IL power. This circuit can source a max-

imum of 100 mA with a 5 V supply. For precision applications,

a voltage reference, such as the ADR421, ADR03, or ADR3420,

can be applied at Terminal A of the digital potentiometer.

PROGRAMMABLE CURRENT SOURCE

A programmable current source can be implemented with the

circuit shown in Figure 45. The load current is the voltage across

Terminal B to Terminal W of the AD5273 divided by RS. At zero

scale, Terminal A of the AD5273 is −2.048 V, which makes the

wiper voltage clamped at ground potential. Depending on the

load, Equation 5 is therefore valid only at certain codes. For

example, when the compliance voltage, VL, equals half of VREF,

the current can be programmed from midscale to full scale of

the AD5273.

Figure 45. Programmable Current Source

(

)

≤

REF

(5)

GAIN CONTROL COMPENSATION

As shown in Figure 46, the digital potentiometers are

commonly used in gain controls or sensor transimpedance

amplifier signal conditioning applications.

Figure 46. Typical Noninverting Gain Amplifier

In both applications, one of the digital potentiometer terminals

is connected to the op amp inverting node with finite terminal

capacitance, C1. It introduces a zero for the 1 βo term with

20 dB/dec, whereas a typical op amp GBP has −20 dB/dec

characteristics. A large R2 and finite C1 can cause this zero’s

frequency to fall well below the crossover frequency. Therefore,

the rate of closure becomes 40 dB/dec and the system has a 0°

phase margin at the crossover frequency. The output may ring,

or in the worst case, oscillate when the input is a step function.

Similarly, it is also likely to ring when switching between two

gain values because this is equivalent to a step change at the

input. To reduce the effect of C1, users should also configure

Terminal B or Terminal A rather than Terminal W at the

inverting node.

GND

VIN

VOUT

AD8601

ADR03

AD5273

SIGNAL

RBIAS

VIN

VOUT

AD5273

U3 2N7002

AD8601

–V

GND

SLEEP

0V TO ...

OUPUT

REF191

1µF

102Ω

100Ω

–2.048 + VL

–5V

OP1177

+5V

V+

V–

AD5273

4.7pF

47k

Ω

100k

Ω

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