AD2437 datasheet(6/42 Pages) AD

6 / 42 page

Rev. 0

Page 6 of 42

July 2023

AD2437

I2S Reduced or Increased Rate

Subordinate transceivers can run the I2S/TDM/PDM interface

at a reduced or increased rate frequency, with respect to the

superframe rate. The reduced rate frequency is derived by divid-

ing the superframe rate from a programmable set of values. The

subordinate transceiver also supports increased sampling rates

of 2× and 4× superframe rates (fSYNCM). Each subordinate node

transceiver can be configured to run at a different I2S/TDM rate.

In reduced rate mode, the transceiver provides an option for a

processor to track the full rate audio frame, which contains new

reduced rate samples. The GPIO7 pin can be used as a strobe,

and the direction can be configured as an input or output.

PULSE DENSITY MODULATION (PDM) INTERFACE

PDM microphones can directly interface to the SIO0/1 pins of

the A2B transceiver. The PDM block on the transceiver converts

a PDM input stream into pulse code modulated (PCM) data for

transmission over the A2B bus, to the local device through the

I2S/TDM port, or both. The PDM interface is available on both

main and subordinate transceivers. It supports high dynamic

range microphones with high signal-to-noise ratio (SNR) and

extended maximum sound pressure level (SPL). The output rate

of the PDM demodulators is controllable at the superframe

(SFF), SFF/2, or SFF/4 rates. In addition, reduced rate modes

support frame rates of SFF/2, SFF/4, SFF/8, SFF/12, SFF/16,

SFF/20, SFF/24, SFF/28, SFF/32, and SFF/128 (for example,

down to 375 Hz for a superframe rate of 48 kHz).

The PDM block supports high pass filtering of the input with a

selectable cut-off frequency including 1, 60, 120, and 240 Hz. A

data is sampled first.

On a subordinate node, either BCLK or GPIO7 can clock PDM

microphones. If GPIO7 is the clock, the BCLK frequency can be

set to a different frequency using the I2S/TDM registers. In this

case, GPIO7 is the PDM clock (PDMCLK) capturing PDM

input on SIO0/SIO1. The clock rate from PDMCLK is 64× the

SYNC frequency. BCLK and GPIO7 can also work concurrently

to clock PDM microphones at the same frequency and phase

alignment, but with opposite polarity.

On a main node, BCLK is always an input, so the clock to PDM

microphones attached to a main node typically come from

GPIO7. It is possible to use BCLK to drive the PDM clock inputs

on a main node, but this restricts the possible TDM settings

because BCLK is required to fall within the specification in

Table 8.

DATA SLOT EXCHANGE BETWEEN SUBORDINATE

NODES

On the DTX pins of the I2S/TDM interface, subordinate trans-

ceivers can selectively output upstream data and downstream

data that originates from other nodes without the need for data

slots routed through the main node. Similarly, RX data channels

from an I2S/TDM frame can become upstream and/or down-

stream slots on the A2B bus and can be received by any node.

I2S TX/RX CROSSBAR

The I2S crossbar provides flexible mapping between channels in

the I2S/TDM interface and slots on the A2B bus.

When a node receives data over the A2B bus and sends it to the

I2S/TDM interface, by default, there is a one-to-one mapping.

For example, the first received slot is mapped to the first chan-

nel on the I2S/TDM interface, and so on. Using the I2S TX

crossbar, the channels on the I2S/TDM interface can be reor-

dered to map to an A2B bus slot for each TDM channel.

Similarly, when a node receives data from the I2S/TDM inter-

face and sends it over the A2B bus, by default, all the received

I2S/TDM channels (defined in the A2B_SLOT registers) are

mapped one-to-one on the A2B bus. Using the I2S RX crossbar,

the TDM channels can be individually selected to send data over

A2B bus slots. For example, only TDM channels marked as valid

are put onto the A2B bus and channels not in use are masked.

See the AD2437A2B Transceiver Technical Reference for details.

SERIAL PERIPHERAL INTERFACE (SPI)

The SPI interface in the transceiver has the following features:

• Master or slave configurable

• Supports up to 3 slave-select outputs

• Up to 12.288 MHz operation

• Programmable clock phase (CPHA) and polarity (CPOL)

• Subordinate transceiver register access

• Local register access

SPI transactions take place between SPI ports of connected

transceivers or between the SPI port and the I2C port of con-

nected transceivers over the A2B bus. The transceiver provides

the ability for SPI communication to occur over the A2B bus

between multiple nodes in a system. The SPI interface is enabled

by default and the transceiver is configured as an SPI slave. To

use the alternative pin functionality, the SPI interface must be

disabled by writing the value 0x02 to the A2B_SPICFG register.

SPI Over Distance

An SPI tunnel is an extension to the A2B protocol where SPI

control and data are exchanged between A2B nodes using dedi-

cated slots on the A2B bus. SPI tunnels are configured and

allocated by the host. SPI over distance supports the following

features:

• Full-duplex read/writes between master and slave

• Up to 256 bytes of pipelined reads

• Extended full-duplex mode with pipelined reads for

more than 256 bytes of data

•Atomic SPI transfer

• Bulk SPI to SPI writes

• Extended bulk SPI writes

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