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SBPH400-3 Fiches technique(PDF) 31 Page - STMicroelectronics

No de pièce SBPH400-3
Description  IEEE1394 3-Port 400Mbps Physical Layer
PDF  43 Pages
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Fabricant  STMICROELECTRONICS [STMicroelectronics]
Site Internet  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

SBPH400-3 Fiches technique(HTML) 31 Page - STMicroelectronics

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timing parameters are given in Table 2.21, and the signal relationships are illustrated in Figure
2.17 and Figure 2.18.
Figure 2.17
PHY-Link reset timing
Figure 2.18
PHY-Link disable timing
Table 2.21
PHY/Link interface reset and disable timing parameters
Symbol
Parameter
Unit
Min
Typ
Max
TLPS_RESET
Time for SBPH400 to recognize LPS logically
deasserted and reset the interface
µs
1.2
2.75
TLPS_DIS
Time for SBPH400 to recognize LPS logically
deasserted and disable the interface
µs25
30
TRESTORE
Time to permit the optional differentiator and
isolation circuits to restore during an interface
reset
µs15
20
SCLK
LPS
LPS
(isolated)
CTL
DATA
LREQ
TLPS_RESET TRESTORE
SCLK
LPS
LPS
(isolated)
CTL
DATA
LREQ
TLPS_DISABLE TRESTORE
2



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