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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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MK50H25PLCC Fiches technique(PDF) 32 Page - STMicroelectronics |
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MK50H25PLCC Fiches technique(HTML) 32 Page - STMicroelectronics |
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32 / 64 page  TP TRANSMIT POLLING TIMER. This scaled timer determines the length of time between polls of the Transmit Descriptor Ring to determine if there is a frame awaiting transmis- sion (i.e. OWNA bit has been set plus other appropriate information placed in the current Transmit Descriptor). Unless TDMD (see CSR0) is set, or a frame is received (in proto- col mode) on the link, no attempt is made to transmit a frame in the Transmit Descriptor Ring until TP expires. At TP expiration all frames available in the Transmit Descriptor Ring will be sent. This field must contain the two’s complement of the period of timer TP. MK50H25 32/64 |
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