RZSLASHG2UL datasheet(57/67 Pages) RENESAS

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RZ/G2UL Group

3. Electrical Characteristics

R01DS0486EJ0110 Rev.1.10

Page 57 of 67

Jun 16, 2025

3.5.16

Serial Communications Interface (SCIg) Access Timing

Table 3.43

SCIg Timing

Item

Symbol

Min.

Max.

Unit

Figures

SCIg

Input clock cycle

Asynchronous

tScyc

—

tp1cyc*1

Figure 3.43

Clocked

synchronous

—

Input clock pulse width

tSCKW

0.4

0.6

tp1cyc*1

Input clock rise time

tSCKr

—

Input clock fall time

tSCKf

—

Output clock cycle

Asynchronous*2

tScyc

—

tp1cyc*1

Clocked

synchronous

—

Output clock pulse width

tSCKW

0.4

0.6

tp1cyc*1

Output clock rise time

tSCKr

—

Output clock fall time

tSCKf

—

Transmit data delay time

Clocked

synchronous

tTXD

—

Figure 3.44

Receive data setup time

Clocked

synchronous

tRXS

—

Receive data hold time

Clocked

synchronous

tRXH

—

Note: AC access timing condition: drive ability 12mA, output load 30pF, slew rate = fast

Note 1.

tp1cyc indicates peripheral clock means SCIn_CLKP (P0ϕ) (n = 0 to 1).

Note 2.

When the SEMR.ABCS0 and SEMR.BGDM bits are set to 1.

SCIn_SCK

(n = 0, 1)

tSCKW

tScyc

tSCKr

tSCKf

Figure 3.43

SCK Input Clock Timing

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