ADSP-21990BBC datasheet(39/50 Pages) AD

39 / 50 page

ADSP-21990

Rev. A

Page 39 of 50

August 2007

JTAG Test And Emulation Port Timing

Table 15 and Figure 18 describe JTAG port operations.

Table 15. JTAG Port Timing

Parameter

Min

Max

Unit

Timing Requirements

tTCK

TCK Period

tSTAP

TDI, TMS Setup Before TCK High

tHTAP

TDI, TMS Hold After TCK High

tSSYS

System Inputs Setup Before TCK Low1

4ns

tHSYS

System Inputs Hold After TCK Low1

5ns

tTRSTW

TRST Pulse Width

4tTCK

Switching Characteristics

tDTDO

TDO Delay from TCK Low

tDSYS

System Outputs Delay After TCK Low3

022

1 System inputs = DATA15–0, ADDR21–0, RD, WR, ACK, BR, BG, PF15–0, DR, TCLK, RCLK, TFS, RFS, CLKIN, RESET.

2 50 MHz maximum.

3 System outputs = DATA15–0, ADDR21–0, MS3–0, RD, WR, ACK, CLKOUT, BG, PF15–0, DT, TCLK0, TCLK, RCLK, TFS, RFS, BMS.

Figure 18. JTAG Port Timing

TMS

TDI

TDO

SYSTEM

INPUTS

SYSTEM

OUTPUTS

TCK

tTCK

tHTAP

tSTAP

tDTDO

tSSYS

tHSYS

tDSYS

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