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M54HC77 Fiches technique(PDF) 1 Page - STMicroelectronics |
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M54HC77 Fiches technique(HTML) 1 Page - STMicroelectronics |
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1 / 10 page ![]() 1/10 August 2001 s HIGH SPEED : tPD = 11 ns (TYP.) at VCC = 6V s LOW POWER DISSIPATION: ICC =2µA(MAX.) at TA=25°C s HIGH NOISE IMMUNITY: VNIH = VNIL = 28 % VCC (MIN.) s SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN) s BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL s WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V s PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 77 DESCRIPTION The M74HC77 is an high speed CMOS 4 BIT D TYPE LATCH fabricated with silicon gate C2MOS technology. It contains two groups of 2 bit latches controlled by an enable input (G1 •2 or G3•4). These two latch groups can be used in different circuits. The data applied to the data inputs (1D, 2D, or 3D, 4D) are transferred to the Q outputs (1Q, 2Q, or 3Q, 4Q) respectively when the enable input (G1 •2 or G3•4) is taken high. The Q outputs will follow the data inputs as long as the enable input is kept high. When the enable input is taken low, the information data applied to the data input is retained at the Q outputs. All inputs are equipped with protection circuits against static discharge and transient excess voltage. M74HC77 4 BIT D TYPE LATCH PIN CONNECTION AND IEC LOGIC SYMBOLS ORDER CODES PACKAGE TUBE T & R DIP M74HC77B1R SOP M74HC77M1R M74HC77RM13TR TSSOP M74HC77TTR TSSOP DIP SOP |
Numéro de pièce similaire - M54HC77 |
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Description similaire - M54HC77 |
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