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M7020R Fiches technique(PDF) 39 Page - STMicroelectronics |
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M7020R Fiches technique(HTML) 39 Page - STMicroelectronics |
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39 / 150 page ![]() 39/150 M7020R Figure 21. x68 Table with One Device Table 25. Latency of SEARCH from Instruction to SRAM Access Cycle, 68-bit, 1 Device Table 26. Shift of SSF and SSV from SADR # of devices Max Table Size Latency in CLK Cycles 1 (TLSZ = 00) 32K x 68-bit 4 2–8 (TLSZ = 01) 256K x 68-bit 5 9–31 (TLSZ = 10) 992K x 68-bit 6 HLAT Number of CLK Cycles 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7 Comparand Register (even) Comparand Register (odd) 67 0 K CFG = 00000000 0 1 2 3 32767 (68-bit Configuration) Location address L K Comparand Register (even) 67 0 K GMR 67 0 AI05665 (First matching entry) |
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