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M68AR024D Fiches technique(PDF) 14 Page - STMicroelectronics |
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M68AR024D Fiches technique(HTML) 14 Page - STMicroelectronics |
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14 / 19 page ![]() M68AR024D 14/19 Figure 13. E1 Controlled, Low VCC Data Retention AC Waveforms Figure 14. E2 Controlled, Low VCC Data Retention AC Waveforms Table 9. Low VCC Data Retention Characteristics Note: 1. All other Inputs at VIH ≥ VCCQ –0.2V or VIL ≤ 0.2V. 2. Tested initially and after any design or process changes that may affect these parameters. tAVAV is Read cycle time. 3. No input may exceed VCC +0.2V. Symbol Parameter Test Condition Min Typ Max Unit ICCDR (1) Supply Current (Data Retention) VCC = 1.0V, E1 ≥ VCCQ –0.2V OR E2 ≤ 0.2V OR UB, LB ≥ VCCQ –0.2V, f= 0 0.5 5 µA tCDR (2) Chip deselected to Data Retention Time 0ns tR (2) Operation Recovery Time tAVAV ns VDR (1) Supply Voltage (Data Retention) E1 ≥ VCCQ –0.2V OR E2 ≤ 0.2V OR UB, LB ≥ VCCQ –0.2V, f= 0 1.0 V AI05855 DATA RETENTION MODE tR 1.95V tCDR VCC 1.65V VDR > 1.0V E1 E1 ≥ VDR – 0.2V AI05875 DATA RETENTION MODE 1.95V VCC 1.65V VDR > 1.0V E2 ≤ 0.2V tCDR E2 tR |
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