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PM6670 Fiches technique(PDF) 25 Page - STMicroelectronics |
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PM6670 Fiches technique(HTML) 25 Page - STMicroelectronics |
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25 / 53 page ![]() PM6670 Device description 25/53 Figure 32. "Virtual-ESR" Network The ripple on the COMP pin is the sum of the output voltage ripple and the triangular ripple generated by the Virtual-ESR Network. In fact the Virtual-ESR Network behaves like a another equivalent series resistor RVESR. A good trade-off is to design the network in order to achieve an RVESR given by: Equation 11 where ∆I L is the inductor current ripple and VRIPPLE is the total ripple at the T node, chosen greater than approximately 20mV. The new closed-loop gain depends on CINT. In order to ensure stability it must be verified that: Equation 12 where: Equation 13 and: COMP COMP VSNS C CINT INT R RINT INT C CFILT FILT t VREF C COUT OUT COMP PIN VOLTAGE OUTPUT VOLTAGE C C R R R R11 t t T T NODE VOLTAGE ∆V ∆V2 ESR ESR ∆V1 + - V VREF REF g gm m R RFb1 Fb1 R RFb2 Fb2 Vr Vr + PWM PWM Comparator Comparator I=gm(V1-Vr) V V11 ESR I V R L RIPPLE VESR − ∆ = Vout Vr f 2 g C Z m INT ⋅ ⋅ π > TOT out Z R C 2 1 f ⋅ ⋅ π = |
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