TDA7500A datasheet(25/40 Pages) STMICROELECTRONICS

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TDA7500A

EXTERNAL MEMORY INTERFACE (EMI) SRAM MODE

Figure 12. External Memory Interface SRAM Read Cycle.

Figure 13. External Memory Interface SRAM Write Cycle.

Characteristics

40MHz

Unit

Min.

Max.

Address Valid and CS Assertion Pulse Width

Address Valid to RD or WR Assertion

RD or WR Assertion Pulse Width

RD or WR Negation to RD or WR Assertion

RD or WR Negation to Address not Valid

Address Valid to Input Data Valid

RD Assertion to Input Data Valid

RD Negation to Data Not Valid (Data Hold Time)

Address Valid to WR Negation

Data Setup Time to WR Negation

Data Hold Time from WR Negation

WR Assertion to Data Valid

WR Negation to Data High-Z (Note 1)

WR Assertion to Data Active

add. [7:0]

data

add. [13:8]

SRA_D

[7:0]

SRA_D

[13:8]

ALE

DRD

add. [7:0]

data

add. [13:8]

SRA

[7:0]

SRA

[13:8]

ALE

DWR

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