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M25P40VMP6T Fiches technique(PDF) 27 Page - STMicroelectronics |
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M25P40VMP6T Fiches technique(HTML) 27 Page - STMicroelectronics |
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27 / 34 page ![]() 27/34 M25P05-A Note: 1. tCH + tCL must be greater than or equal to 1/ fC 2. Value guaranteed by characterization, not 100% tested in production. 3. Expressed as a slew-rate. 4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1. tCLQX tHO Output Hold Time 0 ns tHLCH HOLD Setup Time (relative to C) 10 ns tCHHH HOLD Hold Time (relative to C) 10 ns tHHCH HOLD Setup Time (relative to C) 10 ns tCHHL HOLD Hold Time (relative to C) 10 ns tHHQX 2 tLZ HOLD to Output Low-Z 15 ns tHLQZ 2 tHZ HOLD to Output High-Z 20 ns tWHSL 4 Write Protect Setup Time 20 ns tSHWL 4 Write Protect Hold Time 100 ns tDP 2 S High to Deep Power-down Mode 3 µs tRES1 2 S High to Standby Mode without Electronic Signature Read 3 µs tRES2 2 S High to Standby Mode with Electronic Signature Read 1.8 µs tW Write Status Register Cycle Time 5 15 ms tPP Page Program Cycle Time 1.5 5 ms tSE Sector Erase Cycle Time 2 3 s tBE Bulk Erase Cycle Time 3 6 s Test conditions specified in Table 9 and Table 10 Symbol Alt. Parameter Min. Typ. Max. Unit |
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