6.42

13

7005S/L

High-Speed 8K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Feb.14.20

2738 drw 13

tDW

tAPS

(1)

ADDR"A"

tWC

DATAOUT "B"

MATCH

tWP

R/

W"A"

DATAIN "A"

ADDR"B"

tDH

VALID

MATCH

BUSY"B"

tBDA

VALID

tBDD

tDDD

(3)

tWDD

Timing Waveform of Write with Port-to-Port Read with BUSY(2,5)

(M/S = VIH)(4)

NOTES:

1. tWH must be met for both BUSY input (slave) and output (master).

2. BUSY is asserted on Port "B", blocking R/W"B", until BUSY"B" goes HIGH

3. tWB is only for the 'Slave' Version..

NOTES:

1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (slave).

2. CEL = CER = VIL

3. OE = VIL for the reading port.

4. If M/S = VIL (slave), then BUSY is an input (BUSY"A" =VIH), and BUSY"B" = "don't care", for this example.

5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite port "A".

Timing Waveform of Write with BUSY

2738 drw 14

R/

W"A"

BUSY"B"

tWP

tWB

(3)

R/

W"B"

tWH

(1)

(2)