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STTS424E02 Fiches technique(PDF) 3 Page - STMicroelectronics |
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STTS424E02 Fiches technique(HTML) 3 Page - STMicroelectronics |
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3 / 7 page ![]() STTS424E02 Description 3/7 Figure 1. Logic diagram 1. SDA and EVENT are open drain. Figure 2. Connections (DFN8 and TSSOP8) 1. SDA and EVENT are open drain. Table 1. Signal names Pin Symbol Description Direction 1 A0 Serial Bus Address selection pin. Can be tied to VSS or VDD. Input 2 A1 Serial Bus Address selection pin. Can be tied to VSS or VDD. Input 3 A2 Serial Bus Address selection pin. Can be tied to VSS or VDD. Input 4VSS Supply ground 5SDA(1) 1. SDA and EVENT are open drain. Serial Data Input/output 6 SCL Serial Clock Input 7 EVENT(1) Event output pin. Open drain and active-low Output 8VDD Supply power (2.7V to 3.6V) AI12261 SDA(1) VDD STTS424E02 VSS SCL EVENT(1) A2 A1 A0 1 SDA(1) GND SCL EVENT(1) A1 A0 VDD A2 AI12262 2 3 4 8 7 6 5 |
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